On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique

An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. With this technique, the multiplication efficiency and current driving capabtilty are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 ~m X 240 pm. It is operated with a clock frequency of 1 MHz and can supManuscript received December 9, 1975; revised February 18, 1976. This paper is based on part of a presentation entitled “A non-volatile MNOS quad-latch,” which was presented at the First European SolidState Circuits Conference, Canterbury, England, September 2-5, 1975. The author is with the Allen Clark Research Centre, The Plessey Company Ltd., CasweJl, Towcester, Northants., England. MNOS Voltage ply a maximum load current of about 10 NA. The output impedance is 3.2 Mfl. INTRODUCTION ALTHOUGH MNOS technology is now well established for fabricating nonvolatile memory circuits, the relatively high potentials necessary to write or erase information, typically 30-40 V, are an obvious disadvantage. In many applications, the need to generate these voltages has prevented the use of MNOS devices being economically viable, especially when only a few bits of nonvolatile data are required. To overcome this problem, a method of on-chip high-voltage generation using a new voltage multiplier technique has been developed, enabling MNOS circuits to be operated with standard DICKSON: ON-CHIP HIGH-VOLTAGEGENERATION 375